The invention relates to technology for implementing electronic design automation (“EDA”) tools and electronic designs using EDA tools.
An IC is a small electronic device typically formed from semiconductor material. Each IC contains a large number of electronic components, e.g., transistors, that are wired together to create a self-contained circuit device. The components and wiring on the IC are materialized as a set of geometric shapes that are placed and routed on the chip material. During placement, the location and positioning of each geometric shape corresponding to an IC component are identified on the IC layers. During routing, a set of routes are identified to tie together the geometric shapes for the electronic components.
Once the layout is finished, it is verified to make sure it satisfies the design rules, which are typically provided by the foundry that is to manufacture the IC device. This verification process is called Design Rule Check (DRC). The design rules are a set of rules regarding minimum distances, sizes, enclosure criteria, among other constraints for implementing the layout. The rules are not specifically designed for any particular IC device, but are a compiled set of rules that are applied to all designs to be processed by that fabrication facility for a particular process technology. As such, the design rules are typically configured more conservatively than needed for every single element on an IC. Therefore, strict application of the rules may actually decrease yield for manufacturing of the IC device if portions of the rules are stricter than needed for every given component on an IC.
As the semiconductor industry moves to process technologies of 90 nanometer and below, IC design flows require tools that can carefully consider yield and manufacturability. The emerging state of nanometer semiconductor production demands that designers take yield into consideration up front, rather than leaving it as an expensive and time-consuming afterthought. This has given birth to popular terms like DFM (Design for Manufacturability) and DFY (Design for Yield).
A possible solution that takes yield into account during the IC design flow is to flatten parameterized devices (PMOS/NMOS structures) in the layout to be able to apply preferred rules (DFM Rules) from the foundry on individual structures or local areas. One problem with this approach is that the user can lose backannotation of the impacted devices with their corresponding schematics. Since the parameterized devices get flattened, it creates problems in Engineering Change Order (“ECO”) flow (e.g., using Update Layout Parameters) or while picking any later updates from the schematic automatically. The designer also loses information needed to quickly perform Layout vs Schematic (“LVS”) later in the flow.
Another approach is to maintain separate masters of parameterized devices having different sets of DFM rules. Then, the user can replace masters of specific instances with the desired ones. A problem with this approach is that it can cause great difficulties and costs to maintain different masters of the same device just for having different DFM rules. The user will also need to put extra efforts to maintain correct binding with the schematic for correct backannotation from layout to schematic graphically.
To address these issues (among others), embodiments of the present invention provide an improved method, system, computer program product, and electronic design structures which provides the flexibility to IC designers to be able to relax the design rules to increase the yield and improve the layout productivity. In some embodiments, automated interactive aids and batch tools are provided which can assist in optimizing the final layouts for yield at the initial placement and/or routing stages for optimizing yield. Provided in some embodiments are automated capability to layout designers at the mos devices level to configure mos devices as per different DFY recommendations from the foundry without negative effects on the overall chip area (or cell size). The design rules may be relaxed selectively on an instance basis and wherever possible or desirable.